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Multimillion-gate, low-power Mobile WiMAX design

Beceem Communications has achieved first-pass silicon success on a multimillion-gate, low-power Mobile WiMAX design using Blast Create, Blast Fusion , Blast Plan Pro, Blast Power and Blast Noise.

Magma a provider of semiconductor design software, today announced that Beceem Communications, a leading provider of chipsets for Mobile WiMAX technology, has achieved first-pass silicon success on a multimillion-gate, low-power Mobile WiMAX design using Blast Create, Blast Fusion, Blast Plan Pro, Blast Power and Blast Noise. With Magma's integrated RTL-to-GDSII flow, a small, geographically distributed team of Beceem engineers was able to implement and sign-off on the design 30 percent faster than they had ever done using a conventional point-tool flow. Beceem cellular carrier customers are already testing samples of the Mobile WiMAX integrated circuit (ICs) in their next-generation systems.

'To keep up with the rapidly growing demand for broadband connectivity we need an IC implementation flow that delivers predictability, performance and fast turnaround time,' said Mark Hashemi, vice president of ASIC Engineering at Beceem.

'Magma not only provides us with the best RTL-to-GDSII flow but it provides us with the best support team in the industry; and this has been a key to our success.

Magma's system concurrently addresses timing, power, area and noise, and incorporates key capabilities such as DFT insertion and a sign-off-quality timing into a single environment.

As a result, it was easy for our engineers to learn, there were no iterations between our logic and physical design teams, and they were able to deliver fast and impressive results.' 'As a pioneer in the Mobile WiMAX market Beceem has a very complex and time-sensitive design challenge: to deliver chipsets that can deal with the ever-changing signal conditions in a wireless network,' said Kam Kittrell, Magma's general manager of the Design Implementation Business Unit.

'Beceem's first-pass silicon success demonstrates the ability of the Magma software to address the demands of large, complex designs.' About Magma's RTL-to-GDSII Flow Magma provides a complete RTL-to-GDSII flow within a single executable.

Blast Create and Blast Fusion are the cornerstones of the integrated flow.

Blast Create is an RTL-to-placed-gates system that enables logic designers to synthesize, visualize, evaluate and improve the quality of their RTL code, design constraints, testability requirements and floorplan.

Blast Create integrates fast, full-featured, high-capacity logic and physical synthesis capabilities, full and incremental static timing analysis, design for test (DFT) analysis and synthesis, and power analysis.

Blast Fusion is a physical design solution that includes optimization, place and route, useful skew clock generation, floor planning and power planning, RC extraction and a single, built-in incremental timing analyzer.

Based on Magma's unified data model, Blast Fusion accurately predicts final timing prior to detailed placement, eliminates timing closure iterations and enables rapid design closure, taking into account new nanometer design challenges such as on-chip variation (OCV).

Blast Plan Pro, Blast Power and Blast Noise work in conjunction with Blast Create and Blast Fusion.

The high-capacity hierarchical design planning and prototyping capabilities in Blast Plan Pro enable designers to minimize the cycle time for top-level analysis and optimization on large and complex designs.

Blast Plan Pro leverages Magma's unique GlassBox modeling technology to retain the relevant timing information in each block, allowing full optimization with minimal data.

With Blast Power, low-power analysis and optimization engines are integrated with - and applied throughout - the entire RTL-to-GDSII flow.

Advanced capabilities are also provided such as MTCMOS switch insertion.

Blast Noise is Magma's complete integrated signal integrity analysis and prevention solution.

Blast Noise works concurrently throughout the implementation flow to automatically analyze and adjust a chip design to avoid crosstalk noise, crosstalk delay and signal electromigration (EM) problems.

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